2022-09-04 22:20:12 +02:00
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#pragma once
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#include "fastfetch.h"
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2025-08-04 14:25:14 +08:00
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#include "modules/cpu/option.h"
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2022-09-04 22:20:12 +02:00
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2025-08-14 09:47:14 +08:00
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#define FF_CPU_TEMP_UNSET (-DBL_MAX)
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2022-09-04 22:20:12 +02:00
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2024-05-18 09:58:04 +08:00
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typedef struct FFCPUCore
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{
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uint32_t freq;
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uint32_t count;
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} FFCPUCore;
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2022-09-04 22:20:12 +02:00
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typedef struct FFCPUResult
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{
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FFstrbuf name;
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FFstrbuf vendor;
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2025-08-23 15:14:57 +08:00
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const char* march; // Microarchitecture
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2022-09-04 22:20:12 +02:00
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2024-11-26 21:37:00 +08:00
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uint16_t packages;
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2022-09-04 22:20:12 +02:00
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uint16_t coresPhysical;
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uint16_t coresLogical;
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uint16_t coresOnline;
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2024-07-17 10:56:30 +08:00
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uint32_t frequencyBase; // GHz
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uint32_t frequencyMax; // GHz
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2022-09-04 22:20:12 +02:00
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2024-05-19 18:23:18 +08:00
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FFCPUCore coreTypes[16]; // number of P cores, E cores, etc.
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2024-05-17 16:14:35 +08:00
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2022-09-04 22:20:12 +02:00
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double temperature;
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} FFCPUResult;
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2023-06-24 10:59:53 +08:00
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const char* ffDetectCPU(const FFCPUOptions* options, FFCPUResult* cpu);
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2024-04-18 16:41:19 +08:00
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const char* ffCPUAppleCodeToName(uint32_t code);
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2024-09-09 20:48:19 +08:00
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const char* ffCPUQualcommCodeToName(uint32_t code);
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2024-08-18 17:26:53 +08:00
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#if defined(__x86_64__) || defined(__i386__)
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#include <cpuid.h>
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2025-08-23 15:14:57 +08:00
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inline static void ffCPUDetectByCpuid(FFCPUResult* cpu)
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2024-08-18 17:26:53 +08:00
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{
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2025-08-23 15:14:57 +08:00
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uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
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if (__get_cpuid(0x16, &eax, &ebx, &ecx, &edx))
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{
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// WARNING: CPUID may report frequencies of efficient cores
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// cpuid returns 0 MHz when hypervisor is enabled
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if (eax) cpu->frequencyBase = eax;
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if (ebx) cpu->frequencyMax = ebx;
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}
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if (__get_cpuid(1, &eax, &ebx, &ecx, &edx))
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{
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// Feature tests (leaf1.ecx, leaf7.ebx)
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bool sse2 = (ecx & bit_SSE2) != 0;
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bool sse4_2 = (ecx & bit_SSE4_2) != 0;
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bool pclmul = (ecx & bit_PCLMUL) != 0;
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bool popcnt = (ecx & bit_POPCNT) != 0;
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bool fma = (ecx & bit_FMA) != 0;
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bool osxsave = (ecx & bit_OSXSAVE) != 0;
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unsigned int eax7 = 0, ebx7 = 0, ecx7 = 0, edx7 = 0;
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__get_cpuid_count(7, 0, &eax7, &ebx7, &ecx7, &edx7);
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bool avx2 = (ebx7 & bit_AVX2) != 0;
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bool bmi2 = (ebx7 & bit_BMI2) != 0;
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bool avx512f = (ebx7 & bit_AVX512F) != 0;
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bool avx512bw = (ebx7 & bit_AVX512BW) != 0;
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bool avx512dq = (ebx7 & bit_AVX512DQ) != 0;
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// OS support for AVX/AVX512: check XGETBV (requires OSXSAVE)
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bool avx_os = false;
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bool avx512_os = false;
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if (osxsave)
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{
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__asm__ __volatile__(
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"xgetbv"
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: "=a"(eax), "=d"(edx)
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: "c"(0)
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:
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);
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uint64_t xcr0 = ((uint64_t)edx << 32) | eax;
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// AVX requires XCR0[1:2] == 11b (XMM and YMM state)
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avx_os = (xcr0 & 0x6ULL) == 0x6ULL;
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// AVX512 requires XCR0[7,5,6] etc. common mask 0xE6 (bits 1,2,5,6,7)
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avx512_os = (xcr0 & 0xE6ULL) == 0xE6ULL;
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}
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cpu->march = "unknown";
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if (avx512f && avx512bw && avx512dq && avx512_os) cpu->march = "x86_64-v4";
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else if (avx2 && fma && bmi2 && avx_os) cpu->march = "x86_64-v3";
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else if (sse4_2 && popcnt && pclmul) cpu->march = "x86_64-v2";
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else if (sse2) cpu->march = "x86_64-v1";
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}
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2024-08-18 17:26:53 +08:00
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}
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#else
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2025-08-23 15:14:57 +08:00
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inline static void ffCPUDetectByCpuid(FFCPUResult* cpu)
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2024-08-18 17:26:53 +08:00
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{
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return "Unsupported platform";
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}
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#endif
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